The scaling of conventional complementary metal-oxide-semiconductor field effect transistor (CMOSFET) faces challenges of rapid increase in power consumption. Tunnel field effect transistor (TFET) is a promising candidate enabling further scaling of power supply voltage without increase of off-state leakage current due to its sub-60 mV/dec subthreshold swing. However, in a vertical TFET, the source and drain are at different horizontal levels, which present various issues. For example, the contacts to the source and drain face more challenge due to the height difference.
Accordingly, there is a need for a structure having vertical TFET device and a method making the same to address above concerns.